翻訳と辞書 Words near each other ・ XEFE ・ Xconomy ・ Xconq ・ XConsortium ・ Xcopilot ・ XCOPY ・ XCOPY deployment ・ XCOR Aerospace ・ XCOR EZ-Rocket ・ XCOR Lynx ・ XCore Open Source License ・ XCore XS1 ・ XCore XS1-AnA ・ XCore XS1-G4 ・ XCore XS1-L1 ・ XCore XS1-SU ・ Xcorps Action Sport TV ・ XCP ・ XCP (Protocol) ・ XCR ・ XCR1 ・ XCRI ・ Xcrosscheckx ・ XCT790 ・ XCubeLabs ・ Xculoc ・ Xcuse Me ・ XCX ・ XD ・ XD engine Dictionary Lists mini英和辞書 mini和英辞書 Webster 1913 Latin-English FOLDOC Wikipedia English ウィキペディア

翻訳と辞書　辞書検索 [ 開発暫定版 ] スポンサード リンク XCore XS1-SU ： ウィキペディア英語版 XCore XS1-SU The XS1-SU〔(【引用サイトリンク】title=XCore XS1-U8A-64-FB96 datasheet )〕〔(【引用サイトリンク】title=XCore XS1-U16A-128-FB217 datasheet )〕 is a family of processors designed by XMOS. It is based on a 32-bit architecture, that runs up to 8 concurrent threads, with built-in Analogue to Digital Converters (ADC), USB 2.0 PHY, oscillator, and power supplies. It has been available since spring 2013 running at 500 MHz. Each thread can run at up to 125 MHz. == Description == The XS1-SU1 comprises a single core processor, a USB PHY, a switch, digital I/O ports, and analogue I/O ports. The execution core has a data path, a memory, and register banks for eight threads. The switches of two or more XS1-SU and Xcore XS1-L processors can be connected using one or more links, whereupon threads on all of the cores can communicate with each other by exchanging messages through the switches. The XCore XS1 instruction set architecture supports 12 general purpose registers per thread. A standard 3-operand instruction set is used for programming the thread. 抄文引用元・出典: フリー百科事典『 ウィキペディア（Wikipedia）』 ■ウィキペディアで「XCore XS1-SU」の詳細全文を読む スポンサード リンク 翻訳と辞書 : 翻訳のためのインターネットリソース Copyright(C) kotoba.ne.jp 1997-2016. All Rights Reserved.